RAM is an essential resource required by computer hardware. When the processor speed has reached the GHz clock frequency, the memory throughput may be a bottleneck to achieve high performance. DRAM can offer a reasonable solution for such data storage. A typical computer system consists of several hardware modules that perform different operations on data. These modules attempt to access data simultaneously. This leads to the need for a memory controller that arbitrates between requests polled by different modules and exploits maximum throughput. The memory controller interfaces DRAM and other subsystems. Therefore, it manages data entering and exiting memory. Access latency or access speed depends solely on the memory controller implementation. The work focuses on the relative study of two memory controllers, namely SDRAM and DDR SDRAM controller. The study includes area, power and timing analysis of both. The Synopsys Design Compiler tool is used to obtain the necessary results. Index Terms: SDRAM, DDR, ASIC, Latency.I. INTRODUCTIONAny computer hardware or generally computer system requires minimum storage. Storage requirements can be met by two different classes of memories, namely Static RAM (SRAM) and Dynamic RAM (DRAM). A flip-flop is used in SRAM to hold information. A single-bit SRAM cell is made up of 6 transistors and stores information as a logic level in a cross-connection of transistors. The advantages of SRAM are no refresh mechanism, low power consumption, and no address multiplexing. This therefore makes it suitable for higher levels of the memory pyramid where memory needs to be fast, such as in notepads. SRAM has the disadvantage of low memory density and high cost. When there are ...... middle of paper ......ecks and a high level on the sys_dly_200us indicates the end of the clock stabilization delay. The initialization sequence starts immediately after the conclusion of clock/power stabilization, then the INIT_FSM will change its state from i_IDLE to the i_NOP state. The initialization FSM will transition from the i_NOP state to the i_PRE state during the next clock cycle. In the i_PRE state, the main control module generates the PRELOAD command and this command is applied to all banks of the device. After the PRELOAD command, INIT_FSM will move to the next state. The next state in the initialization FSM design is two AUTO REFRESH commands. These commands will refresh the DRAM memory. After the two refresh cycles, the initialization FSM will enter the i_MRS state. In this state, the LOAD MODE REGISTER command is generated to configure the SDRAM to a specific operating mode..